Method for forming capacitor of semiconductor device

ABSTRACT

Disclosed is a method for manufacturing a capacitor of a semiconductor device. The method includes the steps of providing a substrate having a storage node plug, forming a PE-TEOS layer and a hard mask exposing a storage node contact area on the substrate, forming a storage node contact having a side profile of a positive and negative pattern through etching the PE-TEOS layer, removing the hard mask by etching-back the hard mask, performing an annealing process with respect to a resultant structure, forming a silicon layer on the silicon substrate, which passes through the annealing process, coating a photoresist film on an entire surface of the substrate, forming a storage node electrode by etching-back the photoresist film and the silicon layer, removing a remaining photoresist film, and forming a dielectric layer and a silicon layer on a storage node electrode structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for forming a semiconductordevice, and more particularly to a method for forming a capacitor of asemiconductor device capable of improving capacitance thereof.

2. Description of the Prior Art

Recently, a PSEUDO SRAM combining a DRAM with a SRAM has been developed.In such a PSEUDO SRAM, a capacitor identical to that of the DRAM isadopted in order to form a device. The capacitor stores electriccharges, and provides the electric charges required for operating asemiconductor device. As semiconductor devices become highly integrated,a size of one unit cell becomes smaller so that capacitance required foroperating the semiconductor devices is gradually increased.

That is, even though there is a demand for reducing a size of thecapacitor as the semiconductor devices are highly integrated, there is alimitation on storage of the electric charges in the capacitor, so it isdifficult to highly integrate the capacitor to match with a size of acell. In order to solve the above-mentioned problem, manufacturers haveproposed various structures for storing electric charges in thecapacitor. For example, in order to increase the electric charges storedin the capacitor, various methods including a method using materialhaving a high dielectric constant, a method reducing a thickness ofdielectric material and a method increasing a surface area of thecapacitor, have been proposed. Recently, a method increasing the surfacearea of a capacitor has mainly been used.

In order to increase the surface area of the capacitor, there has beensuggested a method of increasing a height of the capacitor by using aPE-TEOS (Plasma Enhanced-Tetra Ethyl Ortho Silicate) layer.

FIG. 1 is a plan view showing a growth of a hemispherical grain formedin a normal cell block when a PE-TEOS layer is not subject to anannealing process.

In an SRAM having a peripheral area larger than a peripheral area of aDRAM, when the hemispherical grain is grown in order to increase thesurface area of the capacitor, contaminating materials contained in aPE-TEOS layer, such as carbon, are diffused to an exterior, therebyinterrupting growth of the hemispherical grain in the edge and the testpattern of the cell block, in which the PE-TEOS layer is largelydistributed. Accordingly, it is difficult to increase the capacitance ofthe capacitor.

FIG. 2 is a plan view showing a growth of a hemispherical grain in anedge and a test pattern of a cell block when a PE-TEOS layer is notsubject to an annealing process. As is understood from FIGS. 1 and 2, asize and a density of the hemispherical grain shown in FIG. 2 areinferior to a size and a density of the hemispherical grain shown inFIG. 1.

Accordingly, in order to solve the problem regarding the size anddensity of the hemispherical grain as shown in FIG. 2, after the PE-TEOSlayer is formed, a storage node contact is formed by etching the PE-TEOSlayer by using a hard mask. Then, the annealing process is carried outwith respect to the resultant PE-TEOS layer. Thereafter, a storage nodeelectrode filling the storage node contact, a dielectric layer, and aplate electrode are formed, thereby fabricating the capacitor.

If the annealing process is applied to the PE-TEOS layer in the manneras described above, capacitance uniformity is improved than capacitanceuniformity obtained without performing the annealing process.Accordingly, mean capacitance is increased by about 2.7 F/cell. However,such a capacitance increase is insufficient when considering the growthof the hemispherical grain. That is, if the annealing process is carriedout with respect to the PE-TEOS layer after forming the storage nodecontact, a shrinkage phenomenon of the PE-TEOS layer may occur socapacitance is insufficiently increased.

SUMMARY OF THE INVENTION

Accordingly, the present invention has been made to solve theabove-mentioned problems occurring in the prior art, and an object ofthe present invention is to provide a method for forming a capacitor ofa semiconductor, in which growth of a hemispherical grain is easilyachieved without being interrupted by contaminating materials existingin a PE-TEOS layer forming a height of the capacitor.

Another aspect of the present invention is to provide a method forforming a capacitor of a semiconductor, capable of preventing a TEOSlayer from being shrunk by performing an annealing process with respectto the TEOS layer before etching a storage node contact, and capable ofobtaining sufficient capacitance by preventing capacitance lossresulting from a height reduction of a capacitor.

In order to accomplish this object, there is provided a method formanufacturing a capacitor of a semiconductor device, the methodcomprising the steps of: providing a semiconductor substrate having astorage node plug; sequentially forming a TEOS layer and a hard maskexposing a storage node contact area on the semiconductor substrate;forming a storage node contact having a side profile of a positive andnegative pattern through etching the TEOS layer by using the hard mask;removing the hard mask by etching-back the hard mask whilesimultaneously removing a predetermined part of the storage node plug;performing an annealing process with respect to a resultant structure;forming a silicon layer on the silicon substrate, which passes throughthe annealing process; coating a photoresist film on an entire surfaceof the semiconductor substrate including the silicon layer; forming astorage node electrode of a capacitor by etching-back the photoresistfilm and the silicon layer; removing a remaining photoresist film; andsequentially forming a dielectric layer and a silicon layer for a plateelectrode on a storage node electrode structure.

According to the preferred embodiment of the present invention, the TEOSlayer includes PE-TEOS layer.

According to the preferred embodiment of the present invention, the TEOSlayer is formed with a thickness of about 1500˜2500 nm.

According to the preferred embodiment of the present invention, theannealing process is performed for 30˜60 minutes in a furnace having atemperature of about 650˜750° C. while providing N₂ gas into the furnaceat a speed of 10˜20 slm.

According to the preferred embodiment of the present invention, thesilicon layer is formed by depositing an amorphous silicon layer dopedwith impurities, and an undoped amorphous silicon layer on the siliconsubstrate in-situ at a temperature of about 500˜530° C. after theannealing process is carried out with respect to the silicon substrate.

According to the preferred embodiment of the present invention, theamorphous silicon layer doped with impurities, and the undoped amorphoussilicon layer are formed in a ratio of 1:4 to 1:1.

According to the preferred embodiment of the present invention,impurities are doped into the amorphous silicon layer a rate of1.5˜2.5E21 atoms/cc.

BRIEF DESCRIPTION OF THE DRAWINGS

The above object, features and advantages of the present invention willbe more apparent from the following detailed description taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a plan view showing a growth of a hemispherical grain in anormal cell block when a PE-TEOS layer is not subject to an annealingprocess;

FIG. 2 is a plan view showing a growth of a hemispherical grain in anedge and a test pattern of a cell block when a PE-TEOS layer is notsubject to an annealing process;

FIGS. 3 a to 3 g are views showing a method for forming a capacitor of asemiconductor device according to one embodiment of the presentinvention; and

FIGS. 4 a to 4 g are views showing a method for forming a capacitor of asemiconductor device according to another embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a preferred embodiment of the present invention will bedescribed with reference to the accompanying drawings. In the followingdescription and drawings, the same reference numerals are used todesignate the same or similar components, and so repetition of thedescription on the same or similar components will be omitted.

Hereinafter, a method for forming a capacitor of a semiconductor deviceaccording to one embodiment of the present invention will be explainedwith reference to FIGS. 3 a to 3 g.

FIGS. 3 a to 3 g are views showing a method for forming a capacitor of asemiconductor device according to one embodiment of the presentinvention.

FIGS. 3 a to 3 g are views showing a method for forming a capacitor of asemiconductor device according to another embodiment of the presentinvention.

As shown in FIG. 3 a, the method for forming the capacitor of thesemiconductor device according to another embodiment of the presentinvention include a step of depositing a PE-TEOS layer 4 forming aheight of the capacitor on a semiconductor substrate 1 including a bitline (not shown) and a storage node plug 3, at a thickness of about1,500˜2,500 nm. At this time, the PE-TEOS layer is over-deposited byabout 7˜10% with respect to a target. Then, an annealing process iscarried out with respect to an entire surface of substrate including thePE-TEOS layer 4, so contaminating materials contained in a PE-TEOSlayer, such as carbon, are diffused to an exterior. At this time, theannealing process 20 is performed for 30˜60 minutes in a furnace havinga temperature of about 650˜750° C. while providing N₂ gas into thefurnace at a speed of 10˜20 slm. Accordingly, growth of a hemisphericalgrain can be easily achieved without being interrupted by thecontaminating materials existing in the PE-TEOS layer.

Meanwhile, in FIG. 3 a, a part shown with dotted lines in the PE-TEOSlayer represents a shrinkage portion, which is shrunk by 10% from anoriginal thickness caused by the annealing process. In addition,reference number 2 represents an insulating interlayer.

Thereafter, as shown in FIG. 3 b, a polycrystalline silicon layer 5 fora hard mask is deposited on the PE-TEOS layer 4 with a thickness ofabout 250˜500 nm. At this time, the storage node plug 3 is electricallyconnected to a source (not shown) or a drain (not shown) formed at alower portion of the semiconductor substrate 1. Then, after coating aphotoresist film (not shown) on the polycrystalline silicon layer 5, anexposure and development process is carried out, thereby forming aphotoresist film pattern 6 exposing a storage node contact region (notshown).

Then, as shown in FIG. 3 c, the polycrystalline silicon layer is etchedby using the photoresist film pattern as a mask, thereby forming a hardmask 5 a. After that, the PE-TEOS layer is etched by using the hard mask5 a, thereby forming a storage node contact C2 exposing the storage nodeplug 3. At this time, the photoresist film pattern is removed while theabove etching process is being carried out. In addition, a side profileof the storage node contact C2 may be formed with a positive andnegative pattern by properly controlling the etching process.

Thereafter, as shown in FIG. 3 d, an etch-back process is carried outwith respect to the PE-TEOS layer, thereby removing the hard mask. Whenthe etch-back process is performed, the storage node plug 3 is removedby a predetermined thickness. As a result, a height of the capacitor(storage node contact) is increased.

Then, as shown in FIG. 3 e, a silicon layer 8 is deposited on an entiresurface of the substrate, which has been subject to the annealingprocess. At this time, the silicon layer 8 is formed by depositing anamorphous silicon layer doped with impurities, and an undoped amorphoussilicon layer in-situ at a temperature of about 500˜530° C. In addition,the amorphous silicon layer doped with impurities, and the undopedamorphous silicon layer are formed in a ratio of 1:4 to 1:1. Herein,impurities are doped into the amorphous silicon layer in a rate of1.5˜2.5E21 atoms/cc. The impurities include phosphorous.

Thereafter, a photoresist film 9 is coated on an entire surface of thesubstrate including the amorphous silicon layer 8.

Then, as shown in FIG. 3 f, an etch back process is performed withrespect to the photoresist film and the silicon layer in order toindividually separate the capacitors and to remove a remainingphotoresist film. Reference number 8 a represents the silicon layerremaining after the etch back process has been finished.

Then, as shown in FIG. 3 g, a storage node electrode S2 of the capacitoris formed by growing a hemispherical grain a from the remainingamorphous silicon layer. Thereafter, a dielectric layer 10 and apolycrystalline silicon layer 11 for a plate electrode are sequentiallyformed on the storage node electrode S2, thereby fabricating thecapacitor. At this time, even though it is not shown, a pre-treatmentcleaning process can be carried out with respect to the substrateincluding the remaining amorphous silicon layer by using a mixture ofMH₄OH/H₂O₂/H₂O and DHF (dilute HF) liquid.

According to one embodiment of the present invention, after forming thePE-TEOS layer, an N₂ gas annealing process is carried out with respectto the PE-TEOS layer before performing a process for forming the storagenode contact by etching the PE-TEOS layer, so contaminating materialscontained in a PE-TEOS layer, such as carbon, are diffused to anexterior. Accordingly, a hemispherical grain is easily grown on asurface of the storage node electrode through next processes growing thehemispherical grain. In addition, a height of the capacitor is increasedbecause the storage node plug is partially etched during the etch backprocess for removing the hard mask.

FIGS. 4 a to 4 g are views showing a method for forming a capacitor of asemiconductor device according to another embodiment of the presentinvention.

As shown in FIG. 4 a, the method for forming the capacitor of thesemiconductor device according to one embodiment of the presentinvention includes a step of depositing a PE-TEOS layer 34 forming aheight of the capacitor on a substrate 31 including a storage node plug33, at a thickness of about 1,500˜2,500 nm. Thereafter, apolycrystalline silicon layer 35 for a hard mask is deposited on thePE-TEOS layer 34 with a thickness of about 250˜500 nm. At this time, thestorage node plug 33 is electrically connected to a source (not shown)or a drain (not shown) formed at a lower portion of the substrate 1.Reference number 32 is an insulating interlayer.

Then, after coating a photoresist film (not shown) on thepolycrystalline silicon layer 35, an exposure and development process iscarried out, thereby forming a photoresist film pattern 36 exposing astorage node contact region (not shown).

Then, as shown in FIG. 4 b, the polycrystalline silicon layer is etchedby using the photoresist film pattern as a mask, thereby forming a hardmask 35 a. After that, the photoresist film pattern is removed.Subsequently, the PE-TEOS layer is etched by using the hard mask 35 a,thereby forming a storage node contact C3 exposing the storage node plug33. At this time, a side profile of the storage node contact C3 may beformed with a positive and negative pattern by properly controlling theetching process.

Thereafter, as shown in FIG. 4 c, an etch-back process is carried outwith respect to the PE-TEOS layer, thereby removing the hard mask. Whenthe etch-back process is performed, the storage node plug is removed bya predetermined thickness. As a result, a height of the capacitor(storage node contact) is increased.

Then, as shown in FIG. 4 d, an annealing process 50 is carried out withrespect to a resultant structure by using N₂ gas, so contaminatingmaterials contained in a PE-TEOS layer, such as carbon, are diffused toan exterior. Accordingly, growth of a hemispherical grain b can beeasily achieved without being interrupted by the contaminating materialsexisting in the PE-TEOS layer.

At this time, the annealing process 50 is performed for 30˜60 minutes ina furnace having a temperature of about 650˜750° C. while providing N₂gas into the furnace at a speed of 10˜20 slm.

Then, as shown in FIG. 4 e, a silicon layer 38 is deposited on an entiresurface of substrate. the silicon layer 38 is formed by depositing anamorphous silicon layer doped with impurities, and an undoped amorphoussilicon layer in-situ at a temperature of about 500˜530° C. In addition,the amorphous silicon layer doped with impurities, and the undopedamorphous silicon layer are formed in a ratio of 1:4 to 1:1. Herein,impurities are doped into the amorphous silicon layer in a rate of1.5˜2.5E21 atoms/cc. The impurities include phosphorous.

Thereafter, a photoresist film 39 is coated on an entire surface of thesubstrate including the amorphous silicon layer 38.

Then, as shown in FIG. 4 f, an etch back process is performed withrespect to the photoresist film and the silicon layer in order toindividually separate the capacitor, and then, a remaining photoresistfilm is removed. Reference number 38 a represents the silicon layerremaining after the etch back process has been finished.

Then, as shown in FIG. 4 g, a storage node electrode S3 of the capacitoris formed by growing a hemispherical grain b from the remainingamorphous silicon layer. Thereafter, a dielectric layer 40 and apolycrystalline silicon layer 41 for a plate electrode are sequentiallyformed on the storage node electrode S3, thereby fabricating thecapacitor.

According to another embodiment of the present invention, contaminatingmaterials existing in a PE-TEOS layer, such as carbon, are diffused toan exterior by performing an anneal process using N₂ gas. Thus, ahemispherical grain is easily grown through next processes. In addition,a height of the capacitor is increased because the storage node plug ispartially etched during the etch back process for removing the hardmask.

As described above, when an etch back process is performed with respectto a hard mask, a storage node plug exposed by a storage node contact isremoved by a predetermined thickness. Accordingly, a height of acapacitor is increased, so that capacitance of the capacitor is alsoincreased.

In addition, according to the present invention, after forming acontact, an annealing process is carried out by using N₂ gas withrespect to a PE-TEOS layer in order to diffuse contaminating materials,such as carbon, to an exterior. Accordingly, since such contaminatingmaterials can be removed according to the present invention, thehemispherical grain can be easily grown from a surface of a storage nodeelectrode through next processes, thereby increasing capacitance of thecapacitor and improving a yield rate.

Meanwhile, according to the present invention, a PE-TEOS layer forincreasing a height of a capacitor is over-deposited by about 7˜10% withrespect to a target and an annealing process is carried out by using N₂gas with respect to the PE-TEOS layer in order to diffuse contaminatingmaterials, such as carbon, to an exterior. Then, a process for forming astorage node contact is carried out by etching the PE-TEOS layer, whichhas been subject to the annealing process. Accordingly, a hemisphericalgrain is easily grown on a surface of the storage node electrode throughnext processes growing the hemispherical grain, thereby increasingcapacitance of the capacitor and improving a yield rate.

Although a preferred embodiment of the present invention has beendescribed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible, without departing from the scope and spirit of the inventionas disclosed in the accompanying claims.

1. A method for manufacturing a capacitor of a semiconductor device, themethod comprising the steps of: i) providing a semiconductor substratehaving a storage node plug; ii) sequentially forming a TEOS layer and ahard mask exposing a storage node contact area on the semiconductorsubstrate; iii) forming a storage node contact having a side profile ofa positive and negative pattern through etching the TEOS layer by usingthe hard mask; iv) removing the hard mask by etching-back the hard maskwhile simultaneously removing a predetermined part of the storage nodeplug; v) performing an annealing process with respect to a resultantstructure; vi) forming a silicon layer on the silicon substrate, whichpasses through the annealing process; vii) coating a photoresist film onan entire surface of the semiconductor substrate including the siliconlayer; viii) forming a storage node electrode of a capacitor byetching-back the photoresist film and the silicon layer; iX) removing aremaining photoresist film; and X) sequentially forming a dielectriclayer and a silicon layer for a plate electrode on a storage nodeelectrode structure.
 2. The method as claimed in claim 1, wherein theTEOS layer includes PE-TEOS layer.
 3. The method as claimed in claim 1,wherein the TEOS layer is formed with a thickness of about 1500˜2500 nm.4. The method as claimed in claim 1, wherein the hard mask is formedwith a thickness of about 250˜500 nm.
 5. The method as claimed in claim1, wherein the annealing process is performed for 30˜60 minutes in afurnace having a temperature of about 650˜750° C. while providing N₂ gasinto the furnace at a speed of 10˜20 slm.
 6. The method as claimed inclaim 1, wherein the silicon layer is formed by depositing an amorphoussilicon layer doped with impurities, and an undoped amorphous siliconlayer on the silicon substrate in-situ at a temperature of about500˜530° C. after the annealing process is carried out with respect tothe silicon substrate.
 7. The method as claimed in claim 6, wherein theimpurities include phosphorous.
 8. The method as claimed in claim 6,wherein the amorphous silicon layer doped with impurities, and theundoped amorphous silicon layer are formed in a ratio of 1:4 to 1:1. 9.The method as claimed in claim 6, wherein the impurities are doped intothe amorphous silicon layer in a rate of 1.5˜2.5E21 atoms/cc.
 10. Amethod for manufacturing a capacitor of a semiconductor device, themethod comprising the steps of: i) providing a semiconductor substratehaving a storage node plug; ii) depositing a TEOS layer on thesemiconductor substrate for ensuring a height of the capacitor; iii)diffusing contaminating materials contained in the TEOS layer to anexterior by performing an annealing process with respect to the TEOSlayer; iv) forming a hard mask exposing a storage node contact area onthe TEOS layer, which passes through the annealing process; v) forming astorage node contact having a side profile of a positive and negativepattern through etching the TEOS layer by using the hard mask; vi)removing the hard mask by etching-back the hard mask; vii) forming asilicon layer on a resultant structure; viii) coating a photoresist filmon an entire surface of the semiconductor substrate including thesilicon layer; ix) forming a storage node electrode of a capacitor byetching-back the photoresist film and the silicon layer; x) removing aremaining photoresist film; and Xi) sequentially forming a dielectriclayer and a silicon layer for a plate electrode on a storage nodeelectrode structure.
 11. The method as claimed in claim 10, wherein theTEOS layer includes PE-TEOS layer.
 12. The method as claimed in claim10, wherein the TEOS layer is over-deposited by about 7˜10% with respectto a target.
 13. The method as claimed in claim 10, wherein the TEOSlayer is formed with a thickness of about 1500˜2500 nm.
 14. The methodas claimed in claim 10, wherein the hard mask is formed with a thicknessof about 250˜500 nm.
 15. The method as claimed in claim 10, wherein theannealing process is performed for 30˜60 minutes in a furnace having atemperature of about 650˜750° C while providing N₂ gas into the furnaceat a speed of 10˜20 slm.
 16. The method as claimed in claim 10, whereinthe silicon layer is formed by depositing an amorphous silicon layerdoped with impurities, and an undoped amorphous silicon layer on theresultant structure in-situ at a temperature of about 500˜530° C. afterthe annealing process is carried out with respect to the siliconsubstrate.
 17. The method as claimed in claim 16, wherein the impuritiesinclude phosphorous.
 18. The method as claimed in claim 16, wherein theamorphous silicon layer doped with impurities, and the undoped amorphoussilicon layer are formed in a ratio of 1:4 to 1:1.
 19. The method asclaimed in claim 16, wherein the impurities are doped into the amorphoussilicon layer in a rate of 1.5˜2.5E21 atoms/cc.
 20. The method asclaimed in claim 16, wherein the etch back process is carried out withrespect to the hard mask until a predetermined part of a storage nodeplug is removed, thereby increasing a height of a capacitor.
 21. Themethod as claimed in claim 10, further comprising a step of performing apre-treatment cleaning process with respect to the substrate includingthe storage node electrode of the capacitor by using a mixture ofMH4OH/H2O2/H2O and DHF (dilute HF) liquid, after a remaining phototesistfilm is removed.
 22. A method for manufacturing a capacitor of asemiconductor device, the method comprising the steps of: i) providing asemiconductor substrate having a storage node plug; ii) depositing aPE-TEOS layer on the semiconductor substrate; iii) forming a hard maskexposing a storage node contact area on the PE-TEOS layer; iv) forming astorage node contact having a side profile of a positive and negativepattern through etching the PE-TEOS layer by using the hard mask; v)removing the hard mask by etching-back the hard mask; vi) forming asilicon layer on a resultant structure; vii) coating a photoresist filmon an entire surface of the semiconductor substrate including thesilicon layer; viii) forming a storage node electrode of a capacitor byetching-back the photoresist film and the silicon layer; iv) removing aremaining photoresist film; v) sequentially forming a dielectric layerand a silicon layer for a plate electrode on a storage node electrodestructure; and vi) performing an annealing process between step ii) andstep iii) or after step v).